Published on Feb 21, 2020
The demand for faster processors, memory and I/O is a familiar refrain in market applications ranging from personal computers and servers to networking systems and from video games to office automation equipment. Once information is digitized, the speed at which it is processed becomes the foremost determinate of product success. Faster system speed leads to faster processing.
Faster processing leads to faster system performance. Faster system performance results in greater success in the marketplace.
This obvious logic has led a generation of processor and memory designers to focus on one overriding objective - squeezing more speed from processors and memory devices. Processor designers have responded with faster clock rates and super pipelined architectures that use level 1 and level 2 caches to feed faster execution units even faster.
Memory designers have responded with dual data rate memories that allow data access on both the leading and trailing clock edges doubling data access. I/O developers have responded by designing faster and wider I/O channels and introducing new protocols to meet anticipated I/O needs. Today, processors hit the market with 2+ GHz clock rates, memory devices provide sub5 ns access times and standard I/O buses are 32- and 64-bit wide, with new higher speed protocols on the horizon.
Increased processor speeds, faster memories, and wider I/O channels are not always practical answers to the need for speed. The main problem is integration of more and faster system elements. Faster execution units, faster memories and wider, faster I/O buses lead to crowding of more high-speed signal lines onto the physical printed circuit board. One aspect of the integration problem is the physical problems posed by speed.
Faster signal speeds lead to manufacturing problems due to loss of signal integrity and greater susceptibility to noise. Very high-speed digital signals tend to become high frequency radio waves exhibiting the same problematic characteristics of high-frequency analog signals. This wreaks havoc on printed circuit board's manufactured using standard, low-cost materials and technologies.
Signal integrity problems caused by signal crosstalk, signal and clock skew and signal reflections increase dramatically as clock speed increases. The other aspect of the integration problem is the I/O bottleneck that develops when multiple high-speed execution units are combined for greater performance. While faster execution units relieve processor performance bottlenecks, the bottleneck moves to the I/O links. Now more data sits idling, waiting for the processor and I/O buses to clear and movement of large amounts of data from one subsystem to another slows down the overall system performance ratings.
This I/O bottleneck constrains system performance, resulting in diminished actual Performance gains as the processor and memory subsystems evolve. Over the past 20 years, a number of legacy buses, such as ISA, VL-Bus, AGP, LPC, PCI-32/33, and PCI-X, have emerged that must be bridged together to support a varying array of devices. Servers and workstations require multiple high-speed buses, including PCI-64/66, AGP Pro, and SNA buses like InfiniBand.
The hodge-podge of buses increases system complexity, adds many transistors devoted to bus arbitration and bridge logic, while delivering less than optimal performance. A number of new technologies are responsible for the increasing demand for additional bandwidth. High-resolution, texture-mapped 3D graphics and high-definition streaming video are escalating bandwidth needs between CPUs and graphics processors.
Technologies like high-speed networking (Gigabit Ethernet, InfiniBand, etc.) and wireless communications (Bluetooth) are allowing more devices to exchange growing amounts of data at rapidly increasing speeds. Software technologies are evolving, resulting in breakthrough methods of utilizing multiple system processors.
As processor speeds rise, so will the need for very fast, high-volume inter-processor data traffic. While these new technologies quickly exceed the capabilities of today's PCI bus, existing interface functions like MP3 audio, v.90 modems, USB, 1394, and 10/100Ethernet are left to compete for the remaining bandwidth. These functions are now commonly integrated into core logic products.
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